The SN74LS191 is a synchronous, reversible 4-bit up/down binary counter. All flip-flops are clocked simultaneously to avoid counting spikes. A LOW on LOAD asynchronously presets the outputs to the data present on inputs A–D. Counting occurs on the LOW-to-HIGH transition of CLK when CTEN is LOW. D/U selects count direction (LOW=up, HIGH=down). RCO and MAX/MIN outputs support cascading for n-bit counters.
Avoid changing DOWN/UP while CLK is LOW to prevent false clocks. A false ripple carry may occur if CLK and CE are LOW and DOWN/UP is HIGH during a LOAD pulse (per datasheet).