CD4046

Texas Instruments, Harris Semiconductor
Logic - PLLs
CMOS Micropower Phase-Locked Loop - low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators with common signal input and common comparator input.

The CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal input and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2).

CD4046B1PHASE PULSES2PHASE COMP I OUT3COMPARATOR IN4VCO OUT5INHIBIT6CI(1)7CI(2)8Vss16Vdd15ZENER14SIGNAL IN13PHASE COMP II OUT12R2 TO Vss11R1 TO Vss10DEMODULATOR OUT9VCO IN
Supply Voltage:
3V - 18V
Package:
16-pin DIP
Max Frequency:
1.4 MHz

Key Features

  • Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5V
  • Operating frequency range up to 1.4 MHz (typ.) at VDD = 10V, R1 = 5 kΩ
  • Low frequency drift: 0.04%/°C (typ.) at VDD = 10V
  • Choice of two phase comparators: Exclusive-OR network (I) and Edge-controlled memory network with phase-pulse output for lock indication (II)
  • High VCO linearity: <1% (typ.) at VDD = 10V
  • VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
  • Source-follower output of VCO control input (Demod. output)
  • Zener diode to assist supply regulation
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • 5-V, 10-V, and 15-V parametric ratings

Applications

  • FM demodulator and modulator
  • Frequency synthesis and multiplication
  • Frequency discrimination
  • Data synchronization
  • Voltage-to-frequency conversion
  • Tone decoding
  • FSK - Modems
  • Signal conditioning
  • Micropower low-frequency synthesizer

Notes

The VCO requires external components: capacitor C1 (≥100 pF at VDD ≥ 5V; ≥50 pF at VDD ≥ 10V) and resistors R1 (5 kΩ ≤ R1, R2, R3 ≤ 1 MΩ). Phase comparator I is an exclusive-OR network, while phase comparator II has edge-controlled memory with phase-pulse output for lock indication.